1. Field of the Invention
The present invention relates to an array substrate for electronic equipment, and more particularly, to an etchant and an etching method for liquid crystal display (LCD) devices.
2. Discussion of the Related Art
In general, metal lines in electronic equipment generally serve to apply signals to electronic elements. However, the metal lines contribute to production costs and stability of the electronic equipment. Accordingly, a material to form the metal lines needs to be inexpensive, have a low electrical resistance, and a high corrosion resistance.
Array substrates are commonly used in LCD devices, wherein performance characteristics and operational properties of the array substrates are partially determined by the material with which individual elements of the array substrates are formed. For example, gate and data lines of the array substrate significantly influence the performance characteristics and operational properties of the array substrate. Although the resistance of the materials used to form the gate and data lines is relatively insignificant in small-sized LCD devices, the resistance of the gate and data lines in large-sized LCD devices is directly dependent upon image quality. Thus, in large-sized LCD devices having high resolution, materials with which to form the gate and data lines includes aluminum (Al) or Al-alloys due to their low electrical resistance.
However, pure aluminum is chemically weak when exposed to acidic processing, and may result in formation of hillocks on surfaces of the gate line and gate electrode during high temperature processing. Furthermore, the occurrence of hillocks may cause extraordinary growth of a gate insulation layer subsequently formed on the gate line and gate electrode. Thus, the gate insulation layer may be destroyed, and an electrical short circuit may be created between the gate electrode and an active layer that is subsequently formed on the gate insulation layer. Accordingly, thin film transistors (TFTs) having gate lines and gate electrodes formed from pure aluminum do not adequately function as switching devices.
FIG. 1 is a perspective view of a transflective LCD device according to the related art. In FIG. 1, a transflective LCD device 11 includes upper and lower substrates G1 and G2 with an interposed liquid crystal layer 70. For example, the upper and lower substrates G1 and G2 are commonly referred to as color filter and array substrates, respectively.
On a surface of a substrate 5 facing the array substrate G2, the color filter substrate G1 sequentially includes a black matrix 6 and a color filter layer 7. The color filter layer 7 includes a matrix array of red (R), green (G), and blue (B) color filters, and the black matrix 6 is disposed among the matrix array of red (R), green (G), and blue (B) color filters, such that each color filter is divided by the black matrix. In addition, a common electrode 18 is disposed on both the color filter layer 7 and the black matrix 6.
On a surface of a substrate 21 facing the upper substrate G1, the array substrate G2 includes an array of TFTs T (in FIG. 2) that function as switching devices. The array of TFTs is formed to correspond to the matrix array of red (R), green (G) and blue (B) color filters, wherein a plurality of gate and data lines 33 and 53 are positioned to cross each other and the TFT T is located near the crossing portion of the gate and data lines 33 and 53. In addition, the lower substrate G2 includes a plurality of pixel regions P that are defined by the crossing of the gate and data lines 33 and 53, wherein a pixel electrode 69 is disposed within the pixel regions P.
FIG. 2 is an enlarged plan view of a portion “S” of FIG. 1 according to the related art. In FIG. 2, the TFT T includes a gate electrode 31, an active layer 39, a source electrode 49, and a drain electrode 51. The gate electrode 31 is elongated from the gate line 33, and the source electrode 49 is elongated from the data line 53. In addition, the active layer is disposed over the gate electrode 31 between the source and drain electrodes 49 and 51, and the drain electrode 51 is spaced apart from the source electrode 49 across the gate electrode 31.
In FIGS. 1 and 2, the common electrode 18 and the pixel electrode 69 are all formed of a transparent conductive material having good light transmissivity, such as indium tin oxide (ITO). The LCD device of FIGS. 1 and 2 utilizes optical anisotropy and polarization characteristics of liquid crystal molecules of the liquid crystal layer 70 to create images, wherein the liquid crystal molecules have specific alignment directions due to their inherent physical properties. Accordingly, since incident light may be refracted by the alignment of the liquid crystal molecules to form the images and the specific alignment directions of the liquid crystal molecules may be modified by application of an electric field, creation of the images may be easily controlled by changing the electric field. In addition, the material for forming the gate and data lines 33 and 53 is significantly important. For example, if the gate and data lines 33 and 53 are formed of a metallic material having a high electrical resistance, signal delays may be generated along the gate and data lines 33 and 53, thereby misaligning the liquid crystal molecules and preventing the images from properly being created. Thus, image resolution of the LCD device may be reduced.
FIG. 3 is a cross sectional view along III-III of FIG. 1 according to the related art. In FIG. 3, a switching region T and a pixel region P are defined on a substrate 21 by the gate electrode 31 and the gate line 33 formed on the substrate 21. For example, the gate line 33 is disposed along a first direction adjacent to the pixel region P, and the gate electrode 31 extends from the gate line 33 into the switching region T. Then, a gate insulating layer 36 is formed on the substrate 21 to cover the gate electrode 31 and the gate line 33, and an active layer 39 of amorphous silicon and an ohmic contact layer 41 of doped amorphous silicon are sequentially formed on the gate insulating layer 36, especially over the gate electrode 31. Next, the source and drain electrodes 49 and 51 are disposed on the ohmic contact layer 41 and spaced apart from each other across the gate electrode 31. Accordingly, the data line 53 is connected to the source electrode 49 and extends on the gate insulating layer 36, and the data line 53 crosses the gate line 33 and defines the pixel region P (in FIG. 1). Next, a portion of the ohmic contact layer 41 between the source and drain electrodes 49 and 51 is eliminated to expose the underlying active layer 39. A passivation layer 59 is formed on the gate insulating layer 36 to cover the source electrode 49, the drain electrode 51, and the data line 53. In addition, the passivation layer 59 has a drain contact hole 61 that exposes a portion of the drain electrode 51. Then, the pixel electrode 69 of a transparent conductive material is formed on the passivation layer 59 within the pixel region P, and contacts the drain electrode 51 through the drain contact hole 61.
In FIG. 3, the gate electrode 31 and the gate line 33 are formed of aluminum (Al) or an aluminum alloy, such as AlNd. However, as previously described, aluminum is chemically weak and causes formation of hillocks. In order to overcome those disadvantages of using aluminum, chromium (Cr) or molybdenum (Mo), each of which has a strong chemical properties in acidic processes, is frequently used for the gate and data lines. However, forming the gate electrode 31 and the gate line 33 of Cr or Mo causes signal delays due to their high electrical resistance. Furthermore, if a double-layered structure of Al and Cr/Mo is used to form the gate and data lines 33 and 53, an etchant for simultaneously etching the double-layered structure is required and a process for etching the double-layered structure must be adjusted. In addition, if a double-layered structure of Al and Cr/Mo is used to form the gate and data lines 33 and 53, and if the Al layer and the Cr/Mo layer are separately etched, two separate process steps are necessary to etch the double-layered structure of Al and Cr/Mo, thereby complicating fabrication processes and decreasing manufacturing yield.